MAX1166BEUP+【PDF 13/15 页】IC ADC 16BIT 165KSPS 20-TSSOP

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Sheet目录2008

9页 10页 11页 12页 [13页]14页 15页

MAX1165/MAX1166

Low-Power, 16-Bit Analog-to-Digital Converter

with Parallel Interface

_______________________________________________________________________________________

Pin Description

PIN

NAME

MAX1165

MAX1166

MAX1165

MAX1166

FUNCTION

D4/D12

Three-State Digital Data Output

D5/D13

Three-State Digital Data Output

D10

D6/D14

Three-State Digital Data Output

D11

D7/D15

Three-State Digital Data Output. D15 is the MSB.

—

D12

—

Three-State Digital Data Output

—

D13

—

Three-State Digital Data Output

—

D14

—

Three-State Digital Data Output

—

D15

—

Three-State Digital Data Output (MSB)

R/C

Read/Convert Input. Power up and put the MAX1165/MAX1166 in acquisition mode

by holding R/C low during the first falling edge of CS. During the second falling

edge of CS, the level on R/C determines whether the reference and reference

buffer power down or remain on after conversion. Set R/C high during the second

falling edge of CS to power down the reference and buffer, or set R/C low to leave

the reference and buffer powered up. Set R/C high during the third falling edge of

CS to put valid data on the bus.

EOC

End of Conversion. EOC drives low when conversion is complete.

AVDD

Analog Supply Input. Bypass with a 0.1F capacitor to AGND.

AGND

Analog Ground. Primary analog ground (star ground).

AIN

Analog Input

AGND

Analog Ground. Connect pin 14 to pin 12 (MAX1165). Connect pin 10 to pin 8

(MAX1166).

REFADJ

Reference Buffer Output. Bypass REFADJ with a 0.1F capacitor to AGND for internal

reference mode. Connect REFADJ to AVDD to select external reference mode.

REF

Reference Input/Output. Bypass REF with a 4.7F capacitor to AGND for internal

reference mode. External reference input when in external reference mode.

—

RESET

Reset Input. Logic high resets the device.

—

HBEN

High-Byte Enable Input. Used to multiplex the 14-bit conversion result:

1: Most significant byte available on the data bus.

0: Least significant byte available on the data bus.

Convert Start. The first falling edge of CS powers up the device and enables

acquire mode when R/C is low. The second falling edge of CS starts conversion.

The third falling edge of CS loads the result onto the bus when R/C is high.

DGND

Digital Ground

DVDD

Digital Supply Voltage. Bypass with a 0.1F capacitor to DGND.

D0/D8

Three-State Digital Data Output

D1/D9

Three-State Digital Data Output

D2/D10

Three-State Digital Data Output

D3/D11

Three-State Digital Data Output

—

Three-State Digital Data Output

—

Three-State Digital Data Output

—

Three-State Digital Data Output

—

Three-State Digital Data Output

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